Two-phase charge transfer device image sensor

ABSTRACT

A charge coupled device capable of operating with two phase clock pulses wherein asymmetrical potential wells are established by the use of channel stoppers which are formed on opposite edges of the charge coupled device and which have restricted portions through which the charges can flow from one storage area to the other. 
     The invention also comprises an information storage device including an array of photosensors with certain photosensors coupled to a particular charge transfer device according to the invention wherein channel stoppers with restricted passages are formed so as to provide asymmetrical charge transfer between the photosensors and various elements of the charge transfer device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to charge coupled devices and inparticular to a novel charge coupled device and information storagedevice for storing and sequentially transferring electronic signals inrepresentative of information.

2. Description of the Prior Art

Charge coupled devices have been well known for storing and transferringcharges in a storage medium by the use of appropriate potentials appliedupon an insulating layer overlying one surface of a medium. For example,the article entitled "Charge Coupled Imaging: State of the Art" whichappeared in Solid State Devices 1973, pages 83 through 107 disclose anumber of charge coupled devices as well as charge coupled imagesensors.

Prior art charge coupled devices have used a plurality of aligned gatesoverlying an insulating layer on a substrate and wherein three phaseclock signals are respectively applied to the gates.

Other charge coupled devices have utilized semiconductors having a layerof insulating material, as for example, silicon dioxide which varies inthickness and upon which aligned pairs of gates are arranged so as tooperate with two phase clock signals.

It has also been known to provide asymmetrical doping under the gates soas to obtain asymmetrical charge distribution in the device. However,the use of three phase clock pulses, varying thickness of the insulatinglayer under the gates and asymmetrical doping results in complicated andexpensive devices and methods particularly for obtaining the varyingthickness of the insulating layer and the asymmetrical doping are verydifficult to perform.

SUMMARY OF THE INVENTION

The present invention comprises a novel charge coupled device capable ofoperating with two phase clock signals and wherein channel stoppers areprovided on opposite sides of the gates in the semiconductor materialwith restricted openings between adjacent storage areas under the gatesso as to provide asymmetrical charge distribution in the charge transferdevice.

In a specific application as an image sensor light sensing elements areprovided adjacent storage elements in charge transfer devices withchannel stoppers arranged so as to prevent charges from passing from alight sensor element to an adjacent light sensor element but whichallows charges to flow from a particular light sensor element to itsassociated storage element and wherein said channel stoppers further areformed so as to provide restricted areas between adjacent storage areasto thus provide asymmetrical charge distribution and charge transfer ina unilateral direction through the storage device upon the applicationof clock signals.

A main object of the invention is to provide a two phase clock typecharge transfer device which is free from the drawbacks of the two phaseand three phase clock type devices of the prior art.

Another object of this invention is to provide an interline transfersystem for a solid state area imaging device using a novel two phaseclock type charge transfer device system.

In the invention a channel stopper region formed in a solid state areaimaging device is used to form an asymmetrical potential well. Also, inthis invention, a potential well can be easily formed without changingthe thickness of the insulated oxide film over the substrate and thedesired asymmetrical potential well can be formed by a channel stopperregion having a predetermined shape.

Other objects, features and advantages of the invention will be readilyapparent from the following description of certain preferred embodimentsthereof taken in conjunction with the accompanying drawings althoughvariations and modifications may be effected without departing from thespirit and scope of the novel concepts of the disclosure and in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art three phase charge coupled device;

FIG. 2 illustrates a prior art two phase charge coupled device;

FIG. 3 is a top plan view of a solid state imaging device;

FIG. 4 is an enlarged plan view illustrating the solid state imagingarea of the invention;

FIG. 5 is a cross-sectional view taken on line A--A of FIG. 4;

FIG. 6A is a cross-sectional view taken on lines c or c' from FIG. 4;

FIG. 6B illustrates the potentials in FIG. 6A;

FIG. 7A is a cross-sectional view taken on line b or b';

FIG. 7B illustrates the potentials in FIG. 7A;

FIG. 8A is a plan view illustrating a portion of FIG. 4;

FIG. 8B is a view illustrating the potential on a line taken on sectionline B--B of FIG. 8A;

FIG. 9 is a partial sectional view illustrating a modification of theinvention;

FIG. 10 is a partial sectional view illustrating a modification of theinvention; and

FIG. 11 is a top plan view illustrating a charge transfer deviceaccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior art charge coupled devices have been either three phase or twophase clock types. FIG. 1 illustrates a prior art three phase clock typetransfer device which comprises a substrate 5 made of, for example,silicon upon which a dielectric layer 6 made of silicon dioxide or somesimilar substance is deposited and a plurality of gate electrodes 7 areformed on the silicon dioxide layer 6 and are arranged in a chargetransfer direction to form a transfer device. Every third gate electrode7 is connected together to provide three sets of electrodes to which areapplied three phase clock voltages φ₁, φ₂ and φ₃ so as to form potentialwells having different depths in the substrate under adjacent gateelectrodes so that electrical charges being stored can be transferredunilaterally through the device. In such a three phase clock type chargetransfer device, however, it is a drawback because the three phase driveis troublesome and the electrical conductive layers for supplying feedvoltage to the gates will have a complicated pattern and in an imagesensing device the number of picture elements per unit area cannot beincreased when forming a solid state area imaging device.

FIG. 2 illustrates another example of charge coupled devices of theprior art utilizing two phase clock drive in which the elements similarto those in FIG. 1 are shown by the same reference numerals but whereinthe dielectric layer 6 is made to have differing thicknesses under thegates 7 so that each gate has a first portion which is over a relativelythin layer of silicon dioxide and second portions which are overrelatively thick portions of silicon dioxide. Such structures allow twophase clock drive which can be applied to alternate electrodes totransfer charge in a unilateral direction because potential wells whichare asymmetrical relative to the charge transfer direction are formed inthe neighborhood of the substrate surface under each electrode 7 due tothe varying thickness of the dielectric 6. With such an arrangement,when two phase clock voltages φ₁ and φ₂ are applied, electrical chargeswill be transferred in one direction. The two phase clock type chargetransfer device described is suitable for use in interline transfersystem solid state imaging devices. Conventional two phase clock typeCTD in which the thickness of the dielectric under each electric is madedifferent at the front and rear portions relative to the charge transferdirection are very difficult to fabricate. Also, other prior art deviceswherein the impurity concentration of the substrate surface under eachelectrode is made to vary between the front and rear edges are known,however, such devices are also very difficult to construct. Furthermore,the miniaturization of such devices is very difficlt due to the varyingthicknesses of the dielectric 6 and/or the variation in the dopingconcentration.

FIG. 3 illustrates a solid state area imaging device using CTD, forexample, using interline transfer system wherein there are disposed in asemiconductor substrate a plurality of island-like light sensingelements 1 which serve as the picture elements and are arranged as shownin FIG. 3. A vertical shift register having CTD construction is disposedat one side of each column of the light sensing elements 1 and a commonhorizontal shift register 3 also having CTD construction is provided atone end of each of the shift registers 2 so as to receive their outputs.The vertical shift registers 2 have transfer portions corresponding tothe respective light sensing elements 1 and signal charges correspondingto the amount of light impinging upon each of the elements 1 aretransferred to corresponding transfer portions of the vertical shiftregisters 2 by a charge transfer device construction illustrated indotted line by 4. The transfer charges are shifted to the horizontalshift register 3 by the vertical shift registers 2 and the signal issuccessively derived from an output terminal t of the horizontal shiftregister 3. These light sensing elements 1, the shift registers 2 and 3are formed on a common semiconductor substrate and the portions betweenadjacent sensing elements 1 and the portions between the light sensingelements and the shift registers which are to be separated from eachother are formed with channel stopper regions which are heavily dopedwith impurities so that they are isolated electrically from each other.The prior art solid state area imaging devices utilize CTD constructionas discussed in the prior art above and have the same defects as suchdevices.

FIGS. 4 and 5 illustrate one example of an interline transfer systemutilizing a solid state area imaging device according to the invention.A silicon substrate 10 of one conductivity type, for example N-typewhich has an impurity concentration of about 10¹⁵ atoms/cm³ has providedon its main surface 10a a plurality of light sensing elements 11arranged in rows and columns so as to provide a light sensing matrix. Aplurality of vertical shift registers 13 are each respectivelyassociated with a column of light sensing elements and are provided withtransfer regions 12 each of which corresponds to a light sensing elementon one side thereof as shown.

Each light sensing element 11 is formed of a region 14 having aconductivity type different from that of the substrate 10 and might, forexample, be P-type and have an impurity concentration of about 10¹⁷ to10¹⁸ atoms/cm³. The regions 14 can be formed by the same diffusionprocess during which the source and drain regions of an output MOStransistor (not shown) is formed and which is provided at the output forexample of the horizontal shift register of the solid state imagingdevice.

In the substrate 10 are also provided channel stopper regions 15 whichmay contain N-type impurity concentration in the order of 10¹⁸ atoms/cm³which concentration is sufficiently higher than that of the substrateand which can be provided from the surface 10a by ion injection methods,selective diffusion methods or similar processes. The channel stopperregions 15 are formed into a pattern such that they surround theperipheries of the respective light sensing elements and shift registers13 except for portions between each light sensing element and itsassociated transfer region 12 of the shift register 13 as well asbetween adjacent transfer regions 12 of each shift register 13. In theexample illustrated in FIG. 4 for example projecting portions 15a of thechannel stopper region 15 project toward a corresponding projectingportion 15a between each light sensing element and its associatedtransfer region 12 so that the light sensng element 11 will not lose itselectrical charge by leakage. In the example illustrated in FIG. 4, itis to be noted that the portions 15a extend toward each other fromopposite sides of the light sensing element 11 but it is to be realizedthat a single projecting portion 15a can extend substantially toward theother side of the channel stopper and only a single projection need beused.

Additionally, second projecting portions 15b are provided which extendfrom each channel stopper region 15 and project between adjacenttransfer regions 12 in each shift register 13 to form therebetween areasof reduced cross-section 16. In the example illustrated in FIG. 4, theportions 15b are formed at both sides of the transfer region and arearranged in the direction of each shift register 13 to form the reducedarea portion 16 between opposite projection parts 15b, respectively.However, it is to be realized that various patterns can be provided soas to form the projection portions 15b at one side thereof of each ofthe regions 12, for example.

As shown in FIG. 5, a dielectric layer such as silicon dioxide 17 isformed on the surface 10a of the substrate 10 and windows 18 can beformed through the dielectric layer 17 and the light sensing element 11can be formed so as to contact the P-type region 14. A plurality oftransfer electrodes 19 (19a, 19b, 19c . . . ) are deposited over thedielectric layer 17 and over the transfer regions 12 of the respectiveshift registers 13 on each row. Each of the electrodes 19a, 19b, 19c . .. is deposited so as to extend over each transfer region aligned in asingle horizontal row as shown in FIG. 4 and covers the transfer regions12 and the regions of reduced areas 16 of the transfer region 12 locatedat its front edge with respect to the charge transfer direction "a". Theelectrodes 19 do not cover the windows 18 of the light sensing elements11.

With the above described construction, when light impinges upon thelight sensing element 11 (the P-type region 14) photoelectrons aregenerated depending on the amount of light and the electrons will escapeinto the channel stopper region 15 or substra te 10 so that a positivehole will be stored in the region 14. However, when electrical charges(positive holes) stored therein exceed a predetermined amount, theexcess charges will escape into the region of the substrate 10. On theother hand, the electrical charges (positive holes) stored in theregions 14 will be transferred to the respective transfer regions 12 ofeach shift registers 13 which are formed corresponding to and adjacentto the light sensing elements 11. In other words, when the electrode 19has applied thereto a predetermined transfer voltage, for example, -15volts, the transfer region 12 will have a potential well which is deeperthan that of the region 14 of the light sensing element and theelectrical charges (positive holes) stored in the region 14 will betransferred to the transfer region 12.

The alternate electrodes 19a, 19c . . . and 19b and 19d . . . will berespectively combined to form two sets of electrodes to which are thenapplied two phase clock voltages φ₁ and φ₂. The voltage of the clockpulses φ₁ and φ₂ will be selected to be lower than the above mentionedtransfer voltage of -15 volts which is transferred from the lightsensing element 11 to the transfer region 12 and may be for example, -10volts. FIGS. 6A and 7A are cross-sectional views respectively taken onchain lines c or c' and b or b' in FIG. 4. Thus, FIG. 6A is across-sectional view through a wide portion of the transfer region 12and FIG. 7A is a cross-sectional view through the restricted portion 16.FIGS. 6B and 7B are views showing the surface potentials at therespective sections during a condition when the electrodes 19b, 19d . .. have applied thereto a clock voltage pulse φ₂. In FIGS. 6B and 7B fulllines illustrate the potentials in the region 12 and the restrictedportion 16 respectively under the electrode 19a and the broken linesillustrated the potentials in the region 12 and restricted portion 16respectively under the electrode 19b to which is applied the clockvoltage pulse φ₂. It will be apparent from these Figures that where thedistance between the channel stoppers 15 is large will have a widerpotential well than the restricted portion or contracted portion 16 formbetween adjacent transfer regions 12 between each of the shift registers13 which will have a shallow potential well due to the influence of thepotential of the channel stopper region 15. Even at the restricted orcontracted portion 16, however, the potential well depths will differ asthe clock voltage is applied are not applied as is apparent from thecomparison between the full line and broken lines in FIG. 7B. Thus, thesurface potential distribution of the regions 12 along their chargetransfer direction will be changed at the front and rear sides in thetransfer direction of the region 12 and will become asymmetrical.

FIG. 8A is a partial plan view of the shift register 13 and wherein theorientation is rotated 90° relative to FIG. 4. FIG. 8B is a viewillustrating the surface potential on the section line B--B whichcorresponds to the chain line d in FIG. 4. In this example, the set ofelectrodes 19b, 19d has applied thereto the clock voltage pulse φ₂. Itis obvious that the potential at the substrate surface under theelectrodes 19b, 19d . . . to which the clock voltage is applied is lowerthan that under the electrodes 19a, 19c . . . but the surface potentialof the restricted or contracted portion 16 under the respectiveelectrodes 19 are higher by Δa and Δb than those of the regions 12 underthe corresponding electrodes 19. Therefore, each region 12 under theelectrodes 19a, 19c . . . will be provided with a potential barrierhaving a height of Δa at its front edge with respect to the chargetransfer direction and hence such an asymmetrical potential well willcause electrical charges to be transferred in a single direction thatis, from each transfer region 12 under the electrode 19a toward thetransfer region 12 under the electrode 19b.

As has been described above, according to the invention the asymmetricalpotential well relative to the charge transfer direction is formed bythe projecting portions 15b of the channel stopper region 15. Therefore,it is not necessary to vary the thickness of the dielectric layer in astep wise manner under each electrode or to change the concentration ofthe substrate surface as is done with prior art devices such asillustrated in FIG. 2. In other words, the two phase clock CTD of thepresent invention can be constructed in a simple manner withoutincreasing the number of fabrication process steps over those of theprior art.

With the above construction, the transfer between adjacent transferregions 12 in the shift register 13 can be accomplished with the clockvoltage pulses φ₁ and φ₂ which are smaller than the voltage for shiftingelectrical charges from the light sensing element 11 to thecorresponding transfer region 12.

If the width of a restricted or contracted portion 26 formed by theprojecting areas 15a of the channel stopper 15 which are projectedtoward the light sensing element 11 and the corresponding region 12 istaken as W_(s) and the width of the contracted part 16 is taken as W_(t)the relationship therebetween can be suitably selected such that W_(s)is exactly equal to 5 μm and W_(t) is exactly equal to 6 μm. With theabove mentioned relationship while the transfer is being carried out inthe shift register 13 the electrical charges will be prevented fromflowing from the light sensing element 11 into the correspondingtransfer region 12 of the shift register 13 or alternatively from theregion 12 into the region 14 of the light sensing element 11. This isbecause of the voltages mentioned above of -10 volts and -15 volts areused as the transfer voltages.

When the light sensing element 11 is composed of a region 14 of P-typewhich is different from the conductivity type of the substrate region asmentioned above, electrical charges which are in excess and are storedtherein will flow into the substrate so that an overflow drain is notnecessary to be specifically provided and thus a space saving results.

In the above described embodiments, the invention is applied to avertical shift register of the interline transfer system solid statearea imaging device. However, the invention can be applied to thehorizontal shift register (output shift register) and also to any othertype of solid state area imaging device or other CTD.

Furthermore, the invention has been described primarily in a case wherethe invention is applied to a surface CTD but it can also be applied toa buried type CTD. Such an example is illustrated in FIGS. 9 and 10wherein a semiconductor substrate 10 of one conductivity type forexample, a N-type silicon substrate can be selectively formed with aregion of other conductivity type or P-type facing its one surface 10asuch that its transfer region 12 and a channel such as a reduced orcontracted portion 16 between adjacent regions 12 should be formed andthe N-type region of the substrate 10 itself can serve as a channelstopper region 15. In FIGS. 9 and 10 the elements corresponding to thoseshown in FIGS. 6A and 7A are indicated by the same reference numeralsand their description will not be repeated.

FIG. 11 illustrates the principles of the invention by using channelstoppers having restricted portions in a charge coupled device.

A substrate 31 has formed therein channel stopper regions 16 and 17which extend along opposite sides thereof and extending portions 18 and19, 21 and 22, 23 and 24, 26 and 27, and 28 and 29 extend, respectively,from the channel stoppers 16 and 17 toward each other as shown. Adielectric layer 30 is formed over the surface of the substrate andchannel stopper regions and electrodes 31 through 34 are formed over thedielectric layer 30 and are provided with input leads 36 through 39 asshown. Alternate leads 36 through 38 receive clock voltage pulses φ₁ andthe remaining alternate electrodes 37 and 39 receive clock voltagepulses φ₂. The device in FIG. 11 receives charges at one end which aretransferred through the device to the other end due to the asymmetricalpotential wells caused by the restricted portions 19, 22, 24, and 27 and18, 21, 23, and 26 for the same reason as described with respect to theembodiments illustrated above. Thus, as shown in FIG. 11 a novel chargecoupled device can be provided without varying the thickness of thedielectric layer and are varying the impurity concentration of thedevice.

It is seen that this invention comprises a new and novel charge transferdevice and although it has been described with respect to preferredembodiments it is not to be so limited as changes and modifications maybe made therein which are within the full intended scope as defined bythe appended claims.

We claim as our invention:
 1. A two phase charge transfer devicecomprising a semiconductor substrate, an insulation layer of uniformthickness formed on said substrate, a shift register having a pluralityof cells formed in said substrate, an input to said shift register andan output to said shift register between which charges flow, a pluralityof aligned electrodes formed over said cells on said insulationlayer.Iadd., each of said cells being associated with a respectiveelectrode, .Iaddend.and means for applying two phase clock signals tosaid aligned electrodes to form potential wells in said cells and toshift said charges, each of said cells comprising a transfer region anda storage region, a transfer region of a cell being located between astorage region of said cell and said input, each of said cells formed ofsaid transfer and storage regions of said substrate having a firstimpurity concentration of one conductivity type and channel stopperregions having a higher second impurity concentration of said oneconductivity type with the regions of said substrate forming saidstorage regions being defined by regions of said first impurityconcentration bordered in a direction transverse to the charge flowdirection by channel stopper regions of said second impurityconcentration, and said transfer regions being defined by regions ofsaid first impurity concentration which are narrower in said transversedirection than said regions of first impurity concentration in saidstorage regions and said regions of said first impurity concentration insaid transfer regions being bordered in said transverse direction bychannel stopper regions of said second impurity concentration higherthan said first impurity concentration to form asymmetrical potentialwells in said cells, the surface potential in a storage region of a cellbeing deeper than that in a transfer region of said cell.
 2. A two phasecharge coupled image sensor comprising a semiconductor substrate, aninsulation layer of uniform thickness formed on said substrate, a shiftregister having a plurality of cells formed in said substrate, aplurality of electrodes formed over said cells on said insulation layerand means for applying two phase clock signals to said electrodes toform potential wells in said cells and to shift charges, each of saidcells comprising first and second transfer regions and a storage region,a plurality of light sensor regions with one of said light sensorregions associated with each cell of said shift register and each lightsensor connected to supply charges to a second transfer region of eachcell, said first transfer regions arranged between said cells to movecharges in a first direction through said shift register and said secondtransfer regions adapted to move charges from said light sensors intosaid storage regions in a direction normal to said first direction, eachof said cells formed of said transfer and storage regions having a firstimpurity concentration of one conductivity type and channel stopperregions having a higher second impurity concentration of said oneconductivity type, said storage regions defined by regions of firstimpurity concentration bordered in both the first and normal directionsby channel stopper regions, said first transfer regions being defined byregions of said first impurity concentration which are narrower in saidnormal direction transverse to said shift register charge flow directionthan said storage regions, said first transfer regions being bordered insaid normal direction by channel stopper regions, said second transferregions being defined by regions of said first impurity concentrationwhich are narrower in said first direction transverse to said chargeflow direction between said light sensors and said storage regions thansaid storage regions, said second transfer regions being bordered insaid first direction by channel stopper regions, asymmetric potentialwells being formed in said cells, the surface potential in a storageregion of a cell being deeper than that in a first transfer region ofsaid cell and deeper than that in a second transfer region of said cell.3. A two phase charge coupled image sensor according to claim 2, whereinsaid second transfer regions are narrower than said first transferregions transverse to the charge flow directions.
 4. A two phase chargecoupled image sensor according to claim 2, wherein said means forshifting charges applies a voltage to said plurality of electrodes toshift charges from said light sensor regions to said storage regionswhich is higher than the voltage applied to said electrodes to shiftcharges from one storage region to an adjacent storage region.
 5. A twophase charge coupled image sensor comprising a semiconductor substrate,an insulation layer of uniform thickness formed on said substrate, aplurality of light sensor regions formed on said substrate in a matrixto define rows and columns, a plurality of shift registers with oneshift register mounted between columns of said light sensors andreceiving charges from said light sensors, each of said shift registershaving a plurality of cells formed in said substrate, each of said cellscomprising first and second transfer regions and a storage region, eachof said light sensors associated with one of said cells and connected tosupply charges to said second transfer region of said cell, said firsttransfer regions of the cells of each shift register arranged betweensaid cells to move charges in a first direction through said shiftregister and said second transfer regions adapted to move charges fromsaid light sensors to said storage regions in a direction normal to saidfirst direction, each of said cells formed of said transfer and storageregions having a first impurity concentration of one conductivity typeand channel stopper regions having a higher second impurityconcentration of said one conductivity type, said storage regionsdefined by regions of first impurity concentration bordered in both thefirst and normal directions by channel stopper regions, said firsttransfer regions being defined by regions of said first impurityconcentration which are narrower in said nomral direction transverse tosaid shift register charge flow direction than said storage regions,said first transfer regions being bordered in said normal direction bychannel stopper regions, said second transfer regions being defined byregions of said first impurity concentration which are narrower in saidfirst direction transverse to said charge flow direction between saidlight sensors and said storage regions than said storage regions, saidsecond transfer regions being bordered in said first direction bychannel stopper regions, a first plurality of electrodes extending onsaid substrate in the row direction with each electrode overlying firstand second transfer regions and a storage region of each shift register,a second plurality of electrodes extending on said substrate in the rowdirection in an alternating arrangement with said first plurality ofelectrodes with each electrode overlying first and second transferregions and a storage region of each shift register, and means forapplying two phase clock signals to said first and second plurality ofelectrodes so as to form asymmetrical potential wells in said cells, thesurface potential in a storage region of a cell being deeper than thatin a first transfer region of said cell and deeper than that in a secondtransfer region of said cell.
 6. A two phase charge coupled image sensoraccording to claim 5 wherein said means for shifting charges applies avoltage to said first and second plurality of electrodes to shiftcharges from said light sensors to said storage regions which is greaterthan the voltage applied to said first and second plurality ofelectrodes to shift charges from one storage region to an adjacentstorage region.
 7. A two phase charge coupled image sensor according toclaim 5 wherein said second transfer regions are narrower than saidfirst transfer regions transverse to the charge flow directions. .Iadd.8. A two phase charge transfer device comprising a semiconductorsubstrate, an insulation layer of uniform thickness formed on saidsubstrate, a shift register having a plurality of cells formed in saidsubstrate, an input to said shift register and an output to said shiftregister between which charges flow, a plurality of aligned electrodesformed over said cells on said insulation layer, each of said cellsbeing associated with a respective electrode, and means for applying twophase clock signals to said aligned electrodes to form potential wellsin said cells and to shift said charges, each of said cells comprising atransfer region and a storage region, a transfer region of a cell beinglocated between a storage region of said cell and said input, each ofsaid cells formed of said transfer and storage regions of said substratehaving a first conductivity type, and channel stopper regions having asecond conductivity type so as to maintain charge carriers in saidtransfer and storage regions, with the regions of said substrate formingsaid storage regions being defined by regions of said first conductivitytype bordered in a direction transverse to the charge flow direction bychannel stopper regions of said second conductivity type, and saidtransfer regions being defined by regions of said first conductivitytype which are narrower in said transverse direction than said regionsof first conductivity type in said storage regions and said regions ofsaid first conductivity type in said transfer regions being bordered insaid transverse direction by channel stopper regions of said secondconductivity type to form asymmetrical potential wells in said cells,the minimum potential in a storage region of a cell being deeper thanthat in a transfer region of said cell. .Iaddend..Iadd.
 9. A two phasecharge coupled image sensor comprising a semiconductor substrate, aninsulation layer of uniform thickness formed on said substrate, a shiftregister having a plurality of cells formed in said substrate, aplurality of electrodes formed over said cells on said insulation layerand means for applying two phase clock signals to said electrodes toform potential wells in said cells and to shift charges, each of saidcells comprising first and second transfer regions and a storage region,a plurality of light sensor regions with one of said light sensorregions associated with each cell of said shift register and each lightsensor connected to supply charges to a second transfer region of eachcell, said first transfer regions arranged between said cells to movecharges in a first direction through said shift register and said secondtransfer regions adapted to move charges from said light sensors intosaid storage regions in a direction normal to said first direction, eachof said cells formed of said transfer and storage regions having a firstconductivity type and a channel stopper region having a secondconductivity type so as to maintain charge carriers in said transfer andstorage regions, said storage regions defined by regions of firstconductivity type bordered in both the first and normal directions bychannel stopper regions, said first transfer regions being defined byregions of said first conductivity type which are narrower in saidnormal direction transverse to said shift register charge flow directionthan said storage regions, said first transfer regions being bordered insaid normal direction by channel stopper regions, said second transferregions being defined by regions of said first conductivity type whichare narrower in said first direction transverse to said charge flowdirection between said light sensors and said storage regions than saidstorage regions, said second transfer regions being bordered in saidfirst direction by channel stopper regions, asymmetrical potential wellsbeing formed in said cells, the minimum potential in a storage region ofa cell being deeper than that in a first transfer region of said celland deeper than that in a second transfer region of said cell..Iaddend..Iadd.
 10. A two phase charge coupled image sensor comprising asemiconductor substrate, an insulation layer of uniform thickness formedon said substrate, a plurality of light sensor regions formed on saidsubstrate in a matrix to define rows and columns, a plurality of shiftregisters with one shift register mounted between columns of said lightsensors and receiving charges from said light sensors, each of saidshift registers having a plurality of cells formed in said substrate,each of said cells comprising first and second transfer regions and astorage region, each of said light sensors associated with one of saidcells and connected to supply charges to said second transfer region ofsaid cell, said first transfer regions of the cells of each shiftregister arranged between said cells to move charges in a firstdirection through said shift register and said second transfer regionsadapted to move charges from said light sensors to said storage regionsin a direction normal to said first direction, each of said cells formedof said transfer and storage regions having a first conductivity typeand channel stopper regions having a second conductivity type so as tomaintain charge carriers in said transfer and storage regions, saidstorage regions defined by regions of said first conductivity typebordered in both the first and normal directions by channel stopperregions, said first transfer regions being defined by regions of saidfirst conductivity type which are narrower in said normal directiontransverse to said shift register charge flow direction than saidstorage regions, said first transfer regions being bordered in saidnormal direction by channel stopper regions, said second transferregions being defined by regions of said first conductivity type whichare narrower in said first direction transverse to said charge flowdirection between said light sensors and said storage regions than saidstorage regions, said second transfer regions being bordered in saidfirst direction by channel stopper regions, a first plurality ofelectrodes extending on said substrate in the row direction with eachelectrode overlying first and second transfer regions and a storageregion of each shift register, a second plurality of electrodesextending on said substrate in the row direction in an alternatingarrangement with said first plurality of electrodes with each electrodeoverlying first and second transfer regions and a storage region of eachshift register, and means for applying two phase clock signals to saidfirst and second plurality of electrodes so as to form asymmetricalpotential wells in said cells, the minimum potential in a storage regionof a cell being deeper than that in a first transfer region of said celland deeper than that in a second transfer region of said cell..Iaddend.